wafer.space Community - 🕰️-analog

Need to make a analog comparator for my next analog layout. Can’t I just re-use my normal opamp schematic for this? As far as I understand, the two are very similar.

6:51 p.m.

Opamp but the output stage is replaced with a schmitt trigger inverter/buffer = comparator

6:51 p.m.

?

6:51 p.m.

Well, maybe not a schmitt trigger depending on the application.

6:52 p.m.

Wait, is there even a difference between the two?

It's the same basic concepts but you optimize for different things.

6:57 p.m.

What are the requirements for your comparator ?

I’m worried about the output not being something I can safely feed into a standard cell because it might settle on a voltage between high and low.

6:59 p.m.

That’s my current concern

7:00 p.m.

I can optimize it for the input voltage ranges I’m using later, when I have some more concrete numbers.

7:01 p.m.

opamps have analog outputs, so can generate non-logic-level voltages

The general idea is you need enough gain so that any voltage difference at the input will result in the output hitting the rails ...

7:02 p.m.

and then ideally some hysteresis so that noise doesn't create a mess if you have slow transitions.

7:02 p.m.

And as you said above, a schmitt trigger is not a bad way to provide both more gain as a second stage and hysteresis.

7:02 p.m.

This is what I did in the comparator for my 555 clone.

7:04 p.m.

But that's highly dependent on the application ... the "comparator" I did on sky 130 ( for high speed differential input ) works differently and just uses positive feedback and 3 stages to have enough gain to force input to a rail.

Alright

7:05 p.m.

I think i’ll look into how to build a schmitt trigger for this

And then the comparator I'm working on now for clocked sampling works yet another way because if you sample at regular interval you can have sample step and amplify step.

7:06 p.m.

What's the application ?

7:08 p.m.

I have a gf180 schmitt inverter there : https://github.com/smunaut/tt_tnt_gf_555/blob/main/xschem/inv_schmitt.sch https://github.com/smunaut/tt_tnt_gf_555/blob/main/mag/inv_schmitt.mag

Overvoltage protection

7:09 p.m.

Sortof, but that’s the basic idea

Tholin

I’m worried about the output not being something I can safely feed into a standard cell because it might settle on a voltage between high and low.

AFAIK the solution to that is to have so many inverters in sequence that noise will make it statistically improbable to end up with metastable voltages at the end. Clocked comparators afaik help a lot for that, btw. You get a deliberate regenerative gain stage, suitable for feeding to a couple stages of DFFs just like you'd have to do for digital signals that cross clock domains btw.

tnt

And then the comparator I'm working on now for clocked sampling works yet another way because if you sample at regular interval you can have sample step and amplify step.

Ohhh, tell what for (if you can); I'm looking mildly anxiously forward to having to do similar but probably substantially more complicated due to needing it to run at probably 16x interleaving

I'm slowly working toward my USB 2.0 HS PHY goal

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capmim*_m4m5_noshield , just checking wafer space support the mim, HRES poly resistor (one additional mask?) and Vt NMOS from s10 of pdk.

It supports :

2 fF/um^2 MiM
1k / sq HRES poly
Native 6.0v nmos

(edited)

tnt

I'm slowly working toward my USB 2.0 HS PHY goal

Do share what you get from that.

6:49 p.m.

[I'll also ask in the substantially non-overlapping chipalooza matrix, as it's more near-term relevant to there; I'll only expect to have such structure for e-test on Run3, but still..] Regarding the C_Offset capacitance digital trim banks: Is that what the sky130 PDK calls "accumulation-mode varactors"? https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#v-accumulation-mode-mos-varactors Do we have an appropriate device on gf180mcuD and/or IHP SG13cmos5L? [edit:]... we do seem to have an SVaricap on IHP SG13cmos5L; not so sure yet about the situation on gf180mcuD. Which isn't helped by my somewhat poor understanding of the supposed behavior of these structures that can't be replicated (properly) by "just" using "normal" PMOS devices in their own dedicated nwell, with their guard ring and that. (edited)

namibj

AFAIK the solution to that is to have so many inverters in sequence that noise will make it statistically improbable to end up with metastable voltages at the end. Clocked comparators afaik help a lot for that, btw. You get a deliberate regenerative gain stage, suitable for feeding to a couple stages of DFFs just like you'd have to do for digital signals that cross clock domains btw.

Ah, but I'd need a clock source for DFFs

Tholin

Ah, but I'd need a clock source for DFFs

What are you trying to lift the signal into then? Or is the purpose of the S that shall consume the comparator feed secret for the time being?

tnt

It supports :

2 fF/um^2 MiM
1k / sq HRES poly
Native 6.0v nmos

(edited)

thanks!

@namibj There are varactor on gf180. All named "moscap".

tnt

@namibj There are varactor on gf180. All named "moscap".

oh. Are they built like the sky130 ones?

Not sure never looked. magic has a pcell.

namibj

Do share what you get from that.

What I'm designing ATM looks basically similar to that drawing, except the input stage is pmos because common mode is very low, so nmos don't work there.

tnt

What I'm designing ATM looks basically similar to that drawing, except the input stage is pmos because common mode is very low, so nmos don't work there.

yeah that aspect in this one is handled by the CTLE preamp section drawn upper left

tnt

What I'm designing ATM looks basically similar to that drawing, except the input stage is pmos because common mode is very low, so nmos don't work there.

https://people.engr.tamu.edu/spalermo/ecen689/lecture10_ee689_rx_circuits.pdf

tnt

What I'm designing ATM looks basically similar to that drawing, except the input stage is pmos because common mode is very low, so nmos don't work there.

Time-interleaved or not for the USB-HS target?

8:40 p.m.

If you happen to have some reading material you can link on the clock recovery part of the subject matter, please do.

Yes, my VCO is running at 240 MHz with 4 phase 0 90 180 270.

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8:41 p.m.

Ok, gotta go sorry ...

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I otherwise feel like I'd put like 4 extra ones next to the time-interleaved full data rate army either in a box or a cross pattern (not sure yet) and adjust to where those offset ones reach a notably-but-limited BER, comparing the information in the digital domain (slow side).

Hi, I am checking a little bit this page: https://mithro.github.io/gf180mcu-project-template/ I have a question about the analog pins: would it be possible to have more using the standard pads? I see that we can have only 6 of them with the 0.5×1 (Half Width) Because we would like to have the chip on board packaging too

My next submission is going to be a entire analog die. So I’m not going to need the LibreLane flow at all. I am going to do the routing to the pads myself, since I need the wires to be quite thick. Not sure how to accomplish this. I’ll keep everyone updated on my progress.

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Brunny

Hi, I am checking a little bit this page: https://mithro.github.io/gf180mcu-project-template/ I have a question about the analog pins: would it be possible to have more using the standard pads? I see that we can have only 6 of them with the 0.5×1 (Half Width) Because we would like to have the chip on board packaging too

I'm not 100% about the power pads, but analog/bidir/input can be changed in the template to whatever you want. You just can't change the pad position/size/number if you want to use the COB packaging. Pretty sure you can change the power pads too, I don't think the COB pcb ties them together. but not 100% on that part

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Honestly, if that was the case, it would not make sense to write down the number of bidir/analog/input pads and power pads inside the project template. But I would be very happy if this is the case

Tholin

My next submission is going to be a entire analog die. So I’m not going to need the LibreLane flow at all. I am going to do the routing to the pads myself, since I need the wires to be quite thick. Not sure how to accomplish this. I’ll keep everyone updated on my progress.

My idea would be to use the flow of librelane for the generation of the pads; if the pads are "free" a possible ideas would be to parallelize these standards pads, like using 2 or more pads for the same signal, and avoid to manually layout them.

Did anyone look at the IOs drivers ? Are the final driver transistors nmos/pmos used as ESD diodes ? I don't see any separate ESD structures.

tnt started a thread. 2026-08-05 2:23 p.m.

Brunny

Honestly, if that was the case, it would not make sense to write down the number of bidir/analog/input pads and power pads inside the project template. But I would be very happy if this is the case

I can say from experience (Run1) and because I also did it for Run2: you can definitely change bidir/analog/input to whatever you want

I think that page you found on Tim's github is just the result of a script that dumps out the default configs for comparison. I wouldn't read too much into it

Brunny

Honestly, if that was the case, it would not make sense to write down the number of bidir/analog/input pads and power pads inside the project template. But I would be very happy if this is the case

Same understanding here, and as @BreakingTaps says you are free to do whatever you want and switch out they types between {analog/bidir/input} just keep the power pins in place for CoB packing.

Great news guys, thanks a lot to both! For the power pins, I have to check their current specifications, I hope they are fine

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Brunny

Great news guys, thanks a lot to both! For the power pins, I have to check their current specifications, I hope they are fine

they're in the PDK on the page for that padring-member-class cell.

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7:11 p.m.

Working comparator

O- oh!

Working oscillator?

Technically, yes

9:47 p.m.

Now, "is it supposed to be an oscillator" is a different and no less interesting question entirely!

I have a feeling the strong ARM latch with it's nominal/supposed output into an RS latch from which the stabilized output can then be recovered afterwards, would also work suitably for this task here, though ofc replacing the strongly regenerative, made possible through clocked gain core of a strong ARM latch with a sufficciently weakly regenerative one that just manages to provide the desired width of dead-band/hysteresis, and is then followed with a sufficcient quantity of differential gain stages to ensure it still correctly/properly operates the RS latch. One would probably need to rely on CMOS inverter [-pair] (weakened by channel elongation to reduce bandwidth to what the following parts can actually utilize, and to curb power waste in that place, unless a current-starved-inverter style turns out to not break the regenerative core's operating principles) inputs in place of the strong ARM latch's natural nmos-diff-pair, but I doubt you need it to resolve double-hysteresis-flip signals (i.e., twice as much input amplitude as would be required to merely meet the input hysteresis, and where one would thus have a fairly weak but reasonably-above-noise-floor input signal) in under 2 ns (let's say 3ns given the use of 5V devices).

Are there any DRC rules dictating a maximum width for a single transistor?

9:12 a.m.

Can I have one wide FET that stretches the entire width of the core area?

Tholin

My next submission is going to be a entire analog die. So I’m not going to need the LibreLane flow at all. I am going to do the routing to the pads myself, since I need the wires to be quite thick. Not sure how to accomplish this. I’ll keep everyone updated on my progress.

I am also still trying to figure out how to go about making an entirely analog die. Any suggestions, @Leo Moser (mole99) ? I want to do the whole core area by hand, only calling upon LibreLane for filler insertion and DRC checks.

Tholin

I am also still trying to figure out how to go about making an entirely analog die. Any suggestions, @Leo Moser (mole99) ? I want to do the whole core area by hand, only calling upon LibreLane for filler insertion and DRC checks.

Well, for the first part you can either use magic or KLayout to draw the layout (I suppose that wasn't the question

), and for the second part you could use a custom LibreLane flow, either through the API or by modifying the flow through the config. The gf180mcu-precheck is basically just that: it first reads in a GDS into LibreLane's current state using a custom step, and then runs e.g. Magic.DRC and KLayout.DRC on it. In your case, you can also add filler generation.

GitHub - wafer-space/gf180mcu-precheck: Precheck for wafer.space MP...

Precheck for wafer.space MPW runs using the gf180mcu PDK - wafer-space/gf180mcu-precheck

Leo Moser (mole99)

Well, for the first part you can either use magic or KLayout to draw the layout (I suppose that wasn't the question

), and for the second part you could use a custom LibreLane flow, either through the API or by modifying the flow through the config. The gf180mcu-precheck is basically just that: it first reads in a GDS into LibreLane's current state using a custom step, and then runs e.g. Magic.DRC and KLayout.DRC on it. In your case, you can also add filler generation.

The problem is that I’d rather not have to figure out how to draw the padring and sealring by hand. I need a template. A gf180-analog-template, if you will :P

9:31 a.m.

I guess a LibreLane flow that aborts after just those steps?

Tholin

The problem is that I’d rather not have to figure out how to draw the padring and sealring by hand. I need a template. A gf180-analog-template, if you will :P

Now I understand! Yes that one already exists, you can find more information on running the flow in the project template README: https://github.com/wafer-space/gf180mcu-project-template#building-a-standalone-padring-for-analog-design

GitHub - wafer-space/gf180mcu-project-template: Project template fo...

Project template for wafer.space MPW runs using the gf180mcu PDK - wafer-space/gf180mcu-project-template

Idk how you manage to always be one step ahead

9:38 a.m.

Thank you

Haha, well, it's a common problem with analog designs. You're welcome!

I think I’m going to go for a quarter slot this time and hope it gets squeezed into some spare space like some projects did on run 2.

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If you have the time to create additional variations of your design, such as half-slot versions, chances are even higher.

That would be a lot of work since I am doing the whole layout by hand, but I can try

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10:12 a.m.

I probably can adapt it quite easily for half-slot, but I’d feel bad taking up a full slot since this is a pretty simple circuit that is already going to have a lot of unused space on the quarter slot.

10:12 a.m.

I think

10:13 a.m.

Most of the die area is going to be a big power FET, but I don’t expect it to be too large.

10:13 a.m.

In typical fashion, I will fill the remaining area with art

10:13 a.m.

Which should be easier this time since I don’t have to worry about keeping LibreLane out of trouble around the artworks.

Tholin

Which should be easier this time since I don’t have to worry about keeping LibreLane out of trouble around the artworks.

Are you also trying to submit this for Chipalooza?

I don’t know what Chipalooza is

@Tim Edwards is hosting Chipalooza, see here for more: https://opencircuitdesign.com/chipalooza/

Huh, interesting

10:26 a.m.

But does look a lot more is involved there

10:26 a.m.

Like, I see a bunch of review steps

You can handle it! Anyway, Chipalooza for GF will launch in a week and I will announce on the Wafer.Space discord.

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I’m reading the FAQ right now. So, I need to make a layout that is integrated onto a multi-project die? (edited)

12:46 p.m.

Hmmm, not sure what I’m building now is suitable, then, but I can maybe take some of its component modules and do something with those.

Tholin

The problem is that I’d rather not have to figure out how to draw the padring and sealring by hand. I need a template. A gf180-analog-template, if you will :P

KLayout has them as PCells. Well, the sealring; you could also take a template GDS and flatten and delete everything but the top metal/pad-opening structures from inside the sealring, leaving only the literal pads themselves (I'd suggest considering to keep the existing via structure of how the pad electrical connection is escaped downwards, as there are some minor DRC aspects around the interaction between (especially upper-level) vias and pads if those pads are wedge-bonded (like all of Run1 has been)

Tholin

I am also still trying to figure out how to go about making an entirely analog die. Any suggestions, @Leo Moser (mole99) ? I want to do the whole core area by hand, only calling upon LibreLane for filler insertion and DRC checks.

For the record, FC01 was done entirely in KLayout using the IEEE Chipathon docker tag. Took me a few tries to get the coordinate origin and exact precise size of the pad ring right, but that was it.